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fn9247 rev 1.00 page 1 of 27 july 28, 2008 fn9247 rev 1.00 july 28, 2008 ISL8102 two-phase buck pwm controller with high current integrated mosf et drivers datasheet the ISL8102 is a two-phase pwm c ontrol ic with integrated mosfet drivers. it provides a precision voltage regulation system for multiple applications including, but not limited to, high current low voltage point-of-load converters, embedded applications and other general purpose low voltage medium to high current applications. the integration of power mosfet drivers into the cont roller ic marks a departure from the separate pwm controller and driver configuration of previous multi-phase produc t families. by reducing the number of external parts, this i ntegration allows for a cost and space saving power management solution. output voltage can be programmed using the on-chip dac or an external preci sion reference. a tw o bit code programs the dac reference to one of 4 p ossible values (0.6v, 0.9v, 1.2v and 1.5v). a unity gain, dif ferential amplifier is provide d for remote voltage sensing, co mpensating for any potential difference between remote an d local grounds. the output voltage can also be of fset through the use of single external resistor. an optional droop func tion is also implemented and can be disabled for applications having less stringent output voltage variation requirements or experiencing less severe step loads. a unique feature of the ISL8102 is the combined use of both dcr and r ds(on) current sensing. load line voltage positioning and overcurrent p rotection are accomplished through continuous inductor dcr current sensing, while r ds(on) current sensing is used for accurate channel-current balance. using both methods of c urrent sampling utilizes the best advantages of each technique. protection features of this c ontroller ic include a set of sophisticated overvoltage a nd overcurrent protection. overvoltage results in the c onverter turning the lower mosfets on to clamp the rising output voltage and protect the load. an ovp output is also provided to drive an optional crowbar device. the overcurrent protection level is set through a single external resistor. other protection features include protection against an open circuit on the remote sensing inputs. combined, these features provide advanced protection for the output load. features ? integrated multi-phase power conversion - 1 or 2 phase operation ? precision output voltage regulation - differential remote voltage sensing - 0.8% system accuracy over-temperature (for ref=0.6v and 0.9v) - 0.5% system accuracy over-temperature (for ref=1.2v and 1.5v) - usable for output volta ges not exceeding 2.3v - adjustable reference-voltage offset ? precision channel current sharing - uses loss-less r ds(on) current sampling ? optional load line (droop) programming - uses loss-less inductor dcr current sampling ? variable gate-drive bias - 5v to 12v ? internal or external reference voltage setting - on-chip adjustable fixed dac reference voltage with 2-bit logic input selects f rom four fixed reference voltages (0.6v, 0.9v, 1.2v, 1.5v) - reference can be changed dynamically - can use an external voltage reference ? overcurrent protection ? multi-tiered overvoltage protection - ovp pin to drive optional crowbar device ? selectable operation frequ ency up to 1.5mhz per phase ? digital soft-start ? capable of start-up in a pre-biased load ? pb-free (rohs compliant) applications ? high current ddr/chipset core voltage regulators ? high current, low voltage dc/dc converters ? high current, low voltage fpga/asic dc/dc converters data sheet july 28, 2008
ISL8102 fn9247 rev 1.00 page 2 of 27 july 28, 2008 pinout ISL8102 (32 ld qfn) top view ordering information part number part marking temp. range (c) package (pb-free) pkg. dwg. # ISL8102crz (note) * ISL8102 crz 0 to +70 32 ld 5x5 qfn l32.5x5 ISL8102irz (note) * ISL8102 irz -40 to +85 32 ld 5x5 qfn l32.5x5 ISL8102eval1 evaluation platform * add -t suffix for tape and r eel. please refer to tb347 for details on reel s pecifications. note: these intersil pb-free plas tic packaged products employ sp ecial pb-free material sets, molding compounds/die attach mater ials, and 100% matte tin plate plus anneal (e3 term ination finish, which is ro hs compliant and compatible with both snpb and pb-free solderin g operations). intersil pb-free products are msl classified at pb-free peak reflow temp eratures that meet or exceed the pb-free requirements of ipc/je dec j std-020. rgnd ref1 ref0 pgood lgate1 boot1 2ph fs isen1 ugate1 phase1 ovp enll boot2 phase2 vsen ocset icomp isum iref lgate2 pvcc isen2 ugate2 dac ref ofst vcc comp fb vdiff droop 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 32 31 30 29 28 27 26 25 9 10111213141516 33 gnd
ISL8102 fn9247 rev 1.00 page 3 of 27 july 28, 2008 block diagram dac dac ref1 ref0 e/a ref fb offset ofst comp isum iref icomp isen amp oc ocset rgnd vsen vdiff 100a +150mv ovp x 0.82 ovp uvp isen1 isen2 channel current sense ? 1 n ? pwm1 ? pwm2 channel current balance through shoot- protection boot1 ugate1 phase1 lgate1 pvcc logic control gate through shoot- protection boot2 ugate2 phase2 lgate2 logic control gate clock and generator sawtooth soft-start and fault logic phase 2 detect vcc reset power-on 0.66v enll fs pgood gnd 0.2v +1v droop ovp 2ph x1 x1
ISL8102 fn9247 rev 1.00 page 4 of 27 july 28, 2008 typical application - ISL8102 pgood vdiff fb comp vcc isen1 ISL8102 ref1 fs ofst ref +12v +12v phase1 ugate1 boot1 lgate1 isen2 phase2 ugate2 boot2 lgate2 isum icomp iref load vsen rgnd ocset ref0 +5v pvcc enll +12v gnd ovp 2ph dac droop
ISL8102 fn9247 rev 1.00 page 5 of 27 july 28, 2008 absolute maximum ratings supply voltage, vcc . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +6v supply voltage, pvcc . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +15v absolute boot voltage, v boot . . . . . . . . gnd - 0.3v to gnd + 36v phase voltage, v phase . . . . . . . . gnd - 0.3v to 15v (pvcc = 12) gnd - 8v (<400ns, 20j) to 24v (<200ns, v boot-phase = 12v) upper gate voltage, v ugate . . . . v phase - 0.3v to v boot + 0.3v v phase - 3.5v (<100ns pulse width, 2j) to v boot + 0.3v lower gate voltage, v lgate . . . . . . . . gnd - 0.3v to pvcc + 0.3v gnd - 5v (<100ns pulse width, 2j) to pvcc+ 0.3v input, output, or i/o voltage . . . . . . . . . gnd - 0.3v to v cc + 0.3v recommended operating conditions vcc supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5v ? 5% pvcc supply voltage . . . . . . . . . . . . . . . . . . . . . . . +5v to 12v ? 5% ambient temperature (ISL8102cr, ISL8102crz) . . . 0c to +70c ambient temperature (ISL8102ir, ISL8102irz) . . .-40c to +85 c thermal information thermal resistance ? ja (c/w) ? jc (c/w) qfn package (notes 1, 2) . . . . . . . . . . 35 5 maximum junction temperature . . . . . . . . . . . . . . . . . . . . . . +150c maximum storage temperature range . . . . . . . . . .-65c to +1 50c pb-free reflow profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/pb-freereflow.asp caution: do not operate at or near the maximum ratings listed fo r extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 1. ? ja is measured in free air with the component mounted on a high e ffective thermal conductivity t est board with direct attach f eatures. see tech brief tb379. 2. for ? jc , the case temp location is the center of the exposed metal p ad on the package underside. electrical specifications recommended operating conditions , unless otherwise specified. p arameters with min and/or max limits are 100% tested at +25c, unless otherwise specified. temperature l imits established by char acterization and are not production tested. parameter test conditions min typ max units bias supply and internal oscillator input bias supply current i vcc ; enll = high - 15 20 ma gate drive bias current i pvcc ; enll = high, all gate outputs open, f sw =250khz -1.53.0ma vcc por (power-on reset) threshold vcc rising 4.25 4.38 4.50 v vcc falling 3.75 3.88 4.00 v pvcc por (power-on reset) threshold pvcc rising 4.25 4.38 4.50 v pvcc falling 3.75 3.88 4.00 v oscillator ramp amplitude (note 3) v p-p -1.50-v maximum duty cycle (note 3) -66.6-% control thresholds enll rising threshold -0.66-v enll hysteresis - 100 - mv comp shutdown threshold comp falling 0.25 0.35 0.5 v reference and dac system accuracy (dac = 0.6v, 0.9v) droop connected to iref -0.8 - 0 .8 % system accuracy (dac = 1.2v, 1.50v) droop connected to iref -0.5 - 0.5 % dac input low voltage (ref0, ref1) --0.4v dac input high voltage (ref0, ref1) 0.8 - - v external reference (note 3) 0.6 - 1.75 v ofs sink current accuracy (negative offset) r ofs = 30k ?? from ofs to vcc 47.5 50.0 52.5 a ofs source current accur acy (positive offset) r ofs = 10k ?? from ofs to gnd 47.5 50.0 52.5 a
ISL8102 fn9247 rev 1.00 page 6 of 27 july 28, 2008 error amplifier dc gain (note 3) r l = 10k to ground - 96 - db gain-bandwidth product (note 3) c l = 100pf, r l = 10k to ground - 20 - mhz slew rate (note 3) c l = 100pf, load = ? 400a - 8 - v/s maximum output voltage load = 1ma 3.90 4.20 - v minimum output voltage load = -1ma - 0.85 1.0 v remote sense differential amplifier input bias current (vsen) (vsen = 1.5v) 49 55 60 a bandwidth (note 3) -20-mhz slew rate (note 3) -8-v/s overcurrent protection ocset trip current 93 100 107 a ocset accuracy oc comparator offset (ocset and isum difference) - 50 5mv icomp offset isen amplifier offset -5 0 5 mv protection undervoltage threshold vsen falling 80 82 84 %dac undervoltage hysteresis vsen rising - 3 - %dac overvoltage threshold while ic disabled 1.62 1.67 1.72 v overvoltage threshold vsen rising dac + 125mv dac + 150mv dac + 175mv v overvoltage hysteresis vsen falling - 50 - mv open sense-line protection thres hold iref rising and falling vdif f + 0.9v vdiff + 1v vdiff + 1.1v v ovp output high drive voltage i ovp = 15ma, vcc = 5v 2.2 3.4 - v switching time ugate rise time (note 3) t rugate; v pvcc = 12v, 3nf load, 10% to 90% - 26 - ns lgate rise time (note 3) t rlgate; v pvcc = 12v, 3nf load, 10% to 90% - 18 - ns ugate fall time (note 3) t fugate; v pvcc = 12v, 3nf load, 90% to 10% - 18 - ns lgate fall time (note 3) t flgate; v pvcc = 12v, 3nf load, 90% to 10% - 12 - ns ugate turn-on non-overlap (note 3) t pdhugate ; v pvcc = 12v, 3nf load, adaptive - 10 - ns lgate turn-on non-overlap (note 3) t pdhlgate ; v pvcc = 12v, 3nf load, adaptive - 10 - ns gate drive resistance (note 4) upper drive source resistance v pvcc = 12v, 150ma source current 1.25 2.0 3.0 ? upper drive sink resistance v pvcc = 12v, 150ma sink current 0.9 1.6 3.0 ? lower drive source resistance v pvcc = 12v, 150ma source current 0.85 1.4 2.2 ? lower drive sink resistance v pvcc = 12v, 150ma sink current 0.60 0.94 1.35 ? over temperature shutdown thermal shutdown setpoint (note 3) - 160 - c thermal recovery setpoint (note 3) - 100 - c note: 3. limits should be considered ty pical and are not production te sted. 4. limits established by characteri zation and are not production tested. electrical specifications recommended operating conditions , unless otherwise specified. p arameters with min and/or max limits are 100% tested at +25c, unless otherwise specified. temperature l imits established by char acterization and are not production tested. (continued) parameter test conditions min typ max units
ISL8102 fn9247 rev 1.00 page 7 of 27 july 28, 2008 timing diagram simplified power system diagram functional pin description vcc (pin 3) bias supply for the ics small-si gnal circuitry. connect this pin to a +5v supply and loca lly decouple using a quality 1.0f ceramic capacitor. pvcc (pin 15) power supply pin for the mosf et drive. this pin can be connected to any voltage from +5v to +12v, depending on the desired mosfet gate drive level. gnd (pin 33) bias and reference g round for the ic. enll (pin 20) this pin is a threshold sensit ive (approximately 0.66v) enable input for the controller. held l ow, this pin disables controlle r operation. pulled high, the pin enables the controller for operation. fs (pin 29) a resistor, placed from fs to g round, will set the switching frequency. refer to equation 33 and figure 24 for proper resistor calculation. 2ph (pin 31) this pin is used to choose between single or two phase operation. tying this pin to vcc allows for 2-phase operation. tying the 2ph pin to gnd causes the controller to operate in a single phase mode. ref0 and ref1 (pins 30, 21) these pins make up the 2-bit in put that selects the fixed dac reference voltage. these pins respond to ttl logic thresholds. the ISL8102 decodes these inputs to establish ugate lgate t flgate t pdhugate t rugate t fugate t pdhlgate t rlgate channel1 +5v in v out q1 q2 ISL8102 dac channel2 q3 q4 +12v in enll pgood 2 ref0,ref1 ovp
ISL8102 fn9247 rev 1.00 page 8 of 27 july 28, 2008 one of four fixed reference vo ltages; see table 1 on page 11 for correspondence between ref0 and ref1 inputs and reference voltage settings. these pins are internally pull ed high, to approximately 1.2v, by 40a (typically) internal c urrent sources; the internal pull-up current decreases t o 0 as the ref0 and ref1 voltages approach the internal pull-up voltage. both ref0 and ref1 pins are compatible w ith external pull-up voltages not exceeding the ics bias voltage (vcc). vsen and rgnd (pins 8, 7) vsen and rgnd are inputs to the precision differential remote-sense amplifier and should be connected to the sense pins of the remote load. icomp, isum, and iref (pins 10, 12, 13) isum, iref, and icomp are the dcr current sense amplifiers negative input, positive input, and output respectively. for accurate d cr current sensing, connect a resistor from each channels phase node to isum and connect iref to the summing point of the output inductors, roughly vout. a parallel r- c feedback circuit connected between isum and icomp will then create a voltage from iref to icomp proportional to the voltage drop across the inductor dcr. this voltage is referred to as the droop voltage and is added to the differential remote-sense amplifiers output. an optional 0.001f to 0.01f ceramic capacitor can be placed from the iref pin to the isum pin t o help reduce common mode noise that might be introduc ed by the layout. droop (pin 11) this pin enables or disables dro op. tie this pin to the icomp pin to enable droop. to disable droop, tie this pin to the iref pin. vdiff (pin 6) vdiff is the output of the differ ential remote-sense amplifier. the voltage on this pin is equal to the difference between vsen and rgnd added to the difference between iref and icomp. vdiff therefore repres ents the vout voltage plus the droop voltage. fb and comp (pins 5, 4) the internal error amplifier s inverting i nput and output respectively. fb is connected t o vdiff through an external r or r-c network depending on the desired type of compensation (type ii or ii i). comp is tied back to fb through an external r-c network to compensate the regulator. dac (pin 32) the dac pin is the direct output of the internal dac. this pin is connected to ref pin using 1k ? to 5k ? resistor, this pin can be left open if an exte rnal reference is used. ref (pin 1) the ref input pin is the positive input of the error amplifier. this pin can be connected to t he dac pin using a resistor (1k ? to 5k ? ) when the internal dac voltage is used as the reference voltage. when an external voltage reference is used, it must be connected directly to the ref pin, while the dac pin is left unconnected. the output voltage will be regulated to th e voltage at the ref pin unless this voltage is greater than the voltage at the dac pin. if an external refer ence is used at thi s pin, its magnitude cannot exceed 1.75v. a capacitor is used between the ref pin and ground to smooth the dac voltage during soft-start. ofst (pin 2) the ofst pin provides a means to program a dc current for generating an offset voltage ac ross the resistor between fb and vdiff. the offset current i s generated via an external resistor and precision internal voltage references. the polarit y of the offset is selected by connecting the resistor to gnd or vcc. for no offset, the ofst pin should be left unconnected. ocset (pin 9) this is the overcurrent set pin. placing a resistor from ocset to icomp, allows a 100a curr ent to flow out of this pin, producing a voltage reference. i nternal circuitry compares the voltage at ocset to the voltage at isum, and if isum ever exceeds ocset, the overcurr ent protection activates. isen1, isen2 (pins 26, 16) these pins are used for balanc ing the channel currents by sensing the current through each channels lower mosfet when it is conducting. connect a resistor between the isen1 and isen2 pins and their re spective phase node. this resistor sets a current proport ional to the current in the lowe r mosfet during its conduction interval. ugate1 and ugate2 (pins 25, 17) connect these pins to the upper mosfets gates. these pins are used to control t he upper mosfets and are monitored for shoot-through prevention purposes. maximum individual channel duty cycle is limited to 66%. boot1 and boot2 (pins 24, 18) these pins provide the bias voltage for the upper mosfets drives. connect these pins to a ppropriately-chosen external bootstrap capacitors. internal bootstrap diodes connected to the pvcc pins provide the nec essary bootstrap charge. phase1 and phase2 (pins 23, 19) connect these pins to the sou rces of the upper mosfets. these pins are the return path for t he upper mosfets drives. lgate1 and lgate2 (pins 27, 14) these pins are used to control the lower mosfets and are monitored for shoot-through prevention purposes. connect these pins to the lower mo sfets gates. do not use
ISL8102 fn9247 rev 1.00 page 9 of 27 july 28, 2008 external series gate resis tors as this might lead to shoot-through. pgood (pin 28) pgood is used as an indication of the end of soft-start. it is an open-drain logic output that is low impedance until the soft-start is completed and v out is equal to the vid setting. once in normal operation pgood indicates whether the output voltage is within specified overvoltage and undervoltage limits. if the output v oltage exceeds these limits or a reset event o ccurs (such as an overcurrent event), pgood becomes high impedance ag ain. the potential at this pin should not exceed that of the potential at vcc pin by more than a typical forward diode drop at any time. ovp (pin 22) overvoltage protection pin. this pin pulls to vcc when an overvoltage conditi on is detect ed. connect this pin to the gate of an scr or mos fet tied across v in and ground to prevent damage to a load device. operation multi-phase power conversion modern low voltage dc/ dc converter load current profiles have changed to the point that the advantages of multiphase power conversion are impossible to ignore. the technical challenges associated with producing a single-phase converter that is bo th cost-effective and thermally viable have forced a change to the cost-saving approach of multiphase. the ISL8102 controller helps simplify implementation by integrating vi tal functions and requiring minimal external components. the block diagram on page 3 provides a top level view of multi-phase power conversion using the ISL8102 controller. interleaving the switching of each ch annel in an ISL8102-based converter is timed to be symme trically out of phase with the other channel. as a result, the two-phase converter has a combined ripple frequency twice the frequency of one of its phases. in addition, the peak -to-peak amplitude of the combined inductor currents is proportionately reduced (equations 1 and 2). increased ripple frequency and lower ripple amplitude generally translate to lowe r per-channel inductance and lower total output capacitance for a given set of performance specifications. figure 1 illust rates the additive effect on output ripple frequency. the two channel currents (i l1 and i l2 ), combine to form the ac ri pple current and the dc load current. the ripple componen t has two times the ripple frequency of each individual channel current. to understand the reduction of ripple current amplitude in the multi-phase circuit, examine the equation representing an individual channel peak-to-peak inductor current. in equation 1, v in and v out are the input and output voltages respectively, l is the single-channel inductor value, and f sw is the switching frequency. the output capacitors conduct the ripple component of the inductor current. in the case of multi-phase converters, the capacitor current is the sum of the ripple currents from each of the individual channels. compare equat ion 1 to the expression for the peak-to-peak current after the summation of n symmetrically phase-shi fted inductor currents in equation 2. peak-to-peak rippl e current decreases by an amount proportional to the number of channels. output voltage ripple is a function o f capacitance, capacitor equivalent series resistance (esr), and inductor ripple current. reducing the inductor ripple current allows the designer to use fewer or less costly output capacitors. another benefit of interleavin g is to reduce input ripple current. input capacitance is determined in part by the maximum input ripple current. multi-phase topologies can improve overall system cost and size by lowering input ripple current and allowing the designer to reduce the cost of input capacitance. the example in f igure 2 illustrates input currents from a two-phase con verter combining to reduce the total input ripple current. figure 1. pwm and inductor-current waveforms for 2-phase converter pwm2 pwm1 i l2 i l1 i l1 + i l2 i pp v in v out C ?? v out ? lf sw v in ?? --------------------------------------------------------- - = (eq. 1) i cpp , v in nv out ? C ?? v out ? lf sw v ? in ? --------------------------------------------------------------- ---- - = (eq. 2)
ISL8102 fn9247 rev 1.00 page 10 of 27 july 28, 2008 figures 25 and 26 in input capacitor selection on page 24 can be used to determ ine the input-capacitor rms current based on load curre nt, duty cycle, a nd the number of channels. they are provided as aids in determining the optimal input capacitor solution. pwm operation the timing of each converter leg is set by the number of active channels. the default channel setting for the ISL8102 is two. one switching cycle is defined as the time between the internal pwm1 pulse termination signals. the pulse termination signal is the inte rnally generated clock signal that triggers the fa lling edge of pwm 1. the cycle time of the pulse termination signal is th e inverse of the switching frequency set by the resistor between the fs pin and ground. each cycle begins when the clock signal commands pwm1 to go low. the pwm1 transition signals the internal channel 1 mosfet driver to t urn off the channel 1 upper mosfet and turn on the chan nel 1 synchronous mosfet. in the default channel configuration, the pwm2 pulse terminates 1/2 of a cycle after the pwm1 pulse. one switching cycle for the ISL8102 is defined as the time between consecutive pwm pulse terminations (turn-off of the upper mosfet on a channel). each cycle begins when a switching clock signal co mmands the upper mosfet to go off. the other channels upper mosfet conduction is terminated 1/ 2 of a cycle later. once a pwm pulse transitions low, it is hel d low for a minimum of 1/3 cycle. this forced off ti me is required to ensure an accurate current sample. current sensing is described in the next section. a fter the forced off time expires, the pwm output is e nabled. the pwm output state is driven by the posit ion of the error ampl ifier output signal, v comp , minus the current correct ion signal relative to the sawtooth ramp as illustrated in figure 3. when the modified v comp voltage crosses the sawtooth ramp, the pwm output transitions high. the internal mosfet driver detects the change in state of the pw m signal and turns off the synchronous mosfet and tur ns on the upper mosfet. the pwm signal will remain high until the pulse termination signal marks the begi nning of the next cycl e by triggering the pwm signal low. single phase operation can be selected by connecting 2ph to gnd. channel current balance one important benefit of multiphase operation is the thermal advantage gained by distributi ng the dissipated heat over multiple devices and greater ar ea. by doing this the designer avoids the complexity of dri ving parallel mosfets and the expense of using exp ensive heat sinks a nd exotic magnetic materials. in order to realize the thermal advantage, it is important that each channel in a multiphase converter be controlled to carry about the same amount of current at any load level. to achieve this, the currents th rough each channel must be sampled every switching cycl e. the sampled currents, i n , from each active channel are summed together and divided by the number of active ch annels. the re sulting cycle average current, i avg , provides a measure of the total load- current demand on th e converter durin g each switching cycle. channel current balance is achieved by comparing the sampled current of each channel to the cycle average current, and making the proper adjustment to each channel pulse width based on the error. intersils patented current balance method is illustrat ed in figure 3, with error correction for channel 1 repres ented. in the fig ure, the cycle average current, i avg , is compared wit h the channel 1 sample, i 1 , to create an error signal i er . the filtered error signal modifies the pulse width commanded by v comp to correct any unbalance and force i er toward zero. the same method for error signal correction is applied to each active channel. current sampling in order to realize proper cu rrent balance, the currents in each channel must be sampled every switching cycle. this sampling occurs during the forced off-time, following a pwm figure 2. channel input currents and input- capacitor rms current for 2-phase converter q1 d-s current q2 d-s current c in current figure 3. channel 1 pwm function and current- balance adjustment ?? n i avg i 2 ? - + + - + - f(s) pwm1 i 1 v comp sawtooth signal i er note: channel 2 is optional. filter to gate control logic
ISL8102 fn9247 rev 1.00 page 11 of 27 july 28, 2008 transition low. during this ti me the current sense amplifier uses the isen inputs to reprod uce a signal proportional to the inductor current, i l . this sensed current, i sen , is simply a scaled version of the inductor current. the sample window opens exactly 1/6 of the switching period, t sw , after the pwm transitions low. the sam ple window then stays open the rest of the switching cycl e until pwm transitions high again, as illustrated in figure 4. the sampled current, a t the end of the t sample , is proportional to the inductor curre nt and is held until the next switching period sample. the sampled current is used only for channel current balance. the ISL8102 sup ports mosfet r ds(on) current sensing to sample each channels current for channel current balance. the internal circuitry, shown in figure 5 represents channel n of an n-channel converter. t his circuitry is repeated for each channel in the converter, but may not be active depending on the status of th e 2ph pin, as described in pwm operati on on page 10. the ISL8102 senses the channe l load current by sampling the voltage across the lower mosfet r ds(on) , as shown in figure 5. a ground-referenced operational amplifier, internal to the ISL8102, is connected to the ph ase node through a resistor, r isen . the voltage across r isen is equivalent to the voltage drop across the r ds(on) of the lower mosfet while it is conducting. the resu lting current into the isen pin is proportional to the channel current, i l . the isen current is sampled and held as describ ed in current sampling on page 10. from figure 5, equation 3 for i n is derived where i l is the channel current. output voltage setting the ISL8102 uses a digital to anal og converter (dac) to generat e a reference voltage based on the logic signals at the ref0 and ref1 pins. the dac decodes the 2-bit logic signals into one of the discrete voltages shown in table 1. each ref0 and ref1 pins are pulled up to an internal 1.2 v voltage by weak current sourc es (40a current, decreasing to 0 as the voltage at the ref0, ref1 pins varies from 0 to the inte rnal 1.2v pull-up voltage). exter nal pull-up resistors or active-hi gh output stages can augment the pull- up current sources, up to a vol tage of 5v. the dac pin must be connected to ref pin th rough a 1kw to 5kw r esistor and a filter capacitor (0.022f) is con nected between ref and gnd. the ISL8102 accommodates the use of external voltage reference connected to ref pin if a differ ent output voltage is required. the dac voltage must be set at least as high as external reference. the error amp internal non invert ing input is the lower of ref or (dac +300mv). a third method for se tting the output voltage is to use a resis tor divider (r p1 , r s1 ) from the output terminal (v out ) to vsen pin to set the output voltage level as s hown in figure 6. this method is good for generating voltages up t o 2.3v (with the ref voltage s et to 1.5v). for this case, the output voltage can be obtained as shown in equation 4. it is recommended to choose re sistor values of less than 500 ? for r s1 and r p1 resistors in order t o get better output voltage dc accuracy. figure 4. sample and hold timing time pwm i l i sen switching period sampling period old sample current new sample current figure 5. ISL8102 internal and external current- sensing circuitry for current balance i n i sen i l x r ds on ?? r isen ------------------------- - = - + isen(n) r isen sample & hold ISL8102 internal circuit external circuit v in channel n upper mosfet channel n lower mosfet - + i l x r ds on ?? i l table 1. ISL8102 dac voltage selection table ref1 ref0 dac 0 0 0.600v 0 1 0.900v 1 0 1.200v 1 1 1.500v i n i l r ds on ?? r isen ---------------------- ? = (eq. 3) v out v ref r s1 r p1 + ?? r p1 --------------------------------- - v ofs v droop C ? ? ? = (eq. 4)
ISL8102 fn9247 rev 1.00 page 12 of 27 july 28, 2008 voltage regulation in order to regulate the output voltage to a specified level, t he ISL8102 uses the integrating compensation network shown in figure 6. this compensation network insures that the steady state error in the output volt age is limited only to the error in the reference voltage (output of the dac or the external voltage reference) and offse t errors in the ofs current source, remote sense and error am plifiers. intersil specifies the guaranteed tolerance of the ISL8102 to include the combined tolerances of each of these elements, except when an external reference or volt age divider is used, then the tolerances of these components has to be taken into account. the ISL8102 incorporates an in ternal differential remote sense amplifier in the feedback path. the amplifier removes the voltage error encountered when measuring the output voltage relative to the cont roller ground reference point, resulting in a more accurate means of sensing output voltage. connect the loads output sense pins to the non-inverting input, vsen, and inverting input, rgnd, of the remote sense amplifier. the droop voltage, v droop , also feeds into the remote sense amplifier. t he remote sense output, v diff , is therefore equal to the sum of the output voltage, v out , and the droop voltage. v diff is connected to the inverting input of the error amplifier through an external resistor. the output of the error amplifier, v comp , is compared to the sawtooth waveform to generate the pwm signals. the pwm signals control the timing of t he internal mosfet drivers and regulate the converter output so that the voltage at fb is equal to the voltage at ref. thi s will regulate the output voltage to be equal to equation 5. the internal and external circuitry that controls voltage regulation is illustrated in figure 6. load-line (droop) regulation in some high current applications, a requirement on a precisely controlled output i mpedance is imposed. this dependence of output voltage o n load current is often termed droop or load line regulation. the droop is an optional feature in the ISL8102. it can be enabled by connecting icomp p in to droop pin as shown in figure 6. to disable it, co nnect the droop pin to iref pin. as shown in figure 6, a voltage, v droop , proportional to the total current in all active channels, i out , feeds into the differential remote-sense amp lifier. the resulting voltage at the output of t he remote-sense amplif ier is the sum of the output voltage and the droop voltage. as equation 5 shows, feeding this voltage into the compensation network causes the regulator to adjust the out put voltage so that its equal t o the reference voltage mi nus the droop voltage. the droop voltage, v droop , is created by sensing the current through the output induc tors. this is accomplished by using a continuous dcr current sensing method. inductor windings have a c haracteristic distributed resistance or dcr (direct current resistance). for simplicity, the inductor dcr is considered as a separate lumped quantity, as shown in figure 7. the channel current, i l , flowing through the inducto r, passes through the dcr. equation 6 shows t he s-domain equivalent voltage, v l , across the inductor. the inductor dcr is important because the voltage dropped across it is proporti onal to the channel c urrent. by using a simple r-c network and a current sense amplifier, as shown in figure 7, the voltage drop across all of the inductors dcrs can be extracted. the output of the current sense amplifier, v droop , can be shown to be prop ortional to the channel currents i l1 and i l2 , shown in equation 7. figure 6. output voltage and load-line regulation with offset adjustment i ofs external circuit ISL8102 internal circuit comp r 2 r 1 fb vdiff vsen rgnd - + v ofs error amplifier - + differential remote-sense amplifier v comp c 1 ref c ref - + vid dac iref droop + - + v droop - + v out - dac icomp + - isum isense amp r p1 r s1 c sum v out v ref v ofs ? v droop C = (eq. 5) v l s ?? i l sl dcr + ? ?? ? = (eq. 6) v droop s ?? sl ? dcr ------------- 1 + ?? ?? sr comp c comp ?? 1 + ?? --------------------------------------------------------------- ----------- r comp r s ----------------------- i l1 i l2 + ?? dcr ?? ? = (eq. 7)
ISL8102 fn9247 rev 1.00 page 13 of 27 july 28, 2008 if the r-c network component s are selected such that the r-c time constant matches the inductor l/dcr time constant, then v droop is equal to the sum of the voltage drops across the individual dcrs , multiplied by a gain. as equation 8 shows, v droop is therefore proportional to the total output current, i out . by simply adjusti ng the value of r s , the load line can be set to any level, giving the converte r the right amount of droop at all load currents. it may also be necessary to compensate for any changes in dcr due to tem perature. these changes cause the load line to be ske wed, and cause the r-c time constant to not match the l/ dcr time constant. if this becomes a problem a simpl e negative temperature coefficient resistor network can be used in the place of r comp to compensate for the rise in dcr due to temperature. output voltage offset programming the ISL8102 allows the desi gner to accurately adjust the offset voltage by connecting a resistor, r ofs , from the ofs pin to vcc or gnd. when r ofs is connected between ofs and vcc, the voltage across it is regulated to 1.5v. this causes a proportional current (i ofs ) to flow into the ofs pin and out of the fb pin. if r ofs is connected to ground, the voltage across it is regulated to 0.5v, and i ofs flows into the fb pin and out of the ofs pin. the offset current flowing through the resistor between vdiff and fb will generate the desired offset voltage which is equal to the product (i ofs x r 1 ). these functions are shown in figures 8 and 9. once the desired output offset voltage has been determined, use the following formulas to set r ofs : for positive offset (connect r ofs to gnd): for negative offset (connect r ofs to vcc): v droop r comp r s --------------------- i out dcr ?? = (eq. 8) figure 7. dcr sensing configuration - + icomp dcr l inductor v out c out i l 1 - + v l (s) dcr l inductor phase 1 phase 2 i l 2 r s r s r comp c comp isum iref ISL8102 - + v droop i out droop c sum (optional) (eq. 9) r ofs 0.5 r 1 ? v offset -------------------------- = ? v offset -------------------------- = e/a fb ofs vcc gnd + - + - 0.5v 1.5v gnd r ofs r 1 vdiff ISL8102 figure 8. positive offset output voltage programming vref v ofs + - i ofs e/a fb ofs vcc gnd + - + - 0.5v 1.5v v cc r ofs r 1 vdiff ISL8102 vref v ofs + - i ofs figure 9. negative offset output voltage programming
ISL8102 fn9247 rev 1.00 page 14 of 27 july 28, 2008 advanced adaptive zero shoot-through deadtime control (patent pending) the integrated drive rs incorporate a unique adaptive deadtime control technique to minimize deadtime, resulting in high efficiency from the reduced fr eewheeling time of the lower mosfet body-diode conduction, and to prevent the upper and lower mosfets from conducting simultaneously. this is accomplished by ensuring eith er rising gate turns on its mosfet with minimum and sufficient delay after the other has turned off. during turn-off of t he lower mosfet, the phase voltage is monitored until it reaches a - 0.3v/+0.8v trip point for a forward/reverse current, at whi ch time the ugate is released to rise. an auto-zero comparator is used to correct the r ds(on) drop in the phase voltage prev enting false detection of the -0.3v phase level during r ds(on) conduction period. in the case of zero current, the ugate is released after 35ns delay of the lgate dropping below 0.5v. d uring the phase detection, the disturbance of lgate falli ng transition on the phase node is blanked out to prevent falsely tripping. onc e the phase is high, the advanced adaptive shoo t-through circuitry monitors the phase and ugate voltages during a pwm falling edge and the subsequent ugate turn-off . if either the ugate falls to less than 1.75v above the ph ase or the phase falls to less than +0.8v, the lgate is released to turn on. internal bootstrap device the two integrated drivers f eature an internal bootstrap schottky diode. simply adding an external capacitor across the boot and phase pins compl etes the bootst rap circuit. the bootstrap function is als o designed to prevent the bootstrap capacitor from ove rcharging due to the large negative swing at the phase node. this reduces voltage stress on the boot to phase pins. the bootstrap capacitor must have a maximum voltage rating above pvcc + 5v and its capacit ance value can be chosen from equation 11. where q g1 is the amount of gate charge per upper mosfet at v gs1 gate-source voltage and n q1 is the number of control mosfets. the ? v boot_cap term is defined as the allowable droop in the rail of t he upper gate drive. figure 10 shows the boot capacitor ripple voltage as a function of boot capacitor value and total upper mosfet gate charge. gate drive voltage versatility the ISL8102 provides the us er flexibility in choosing the gate drive voltage for efficien cy optimization. the controller ties the upper and lower drive rails together. simply applying a voltage from 5v u p to 12v on pvcc s ets both gate drive rail voltages simultaneously. initialization prior to initializat ion, proper conditions must exist on the enll, vcc, pvcc and the ref0 and ref1 pins. when the conditions are met, the controller begins soft-start. once the output voltage is within the proper window of operation, the controller asserts pgood. enable and disable while in shutdown mode, the pwm outputs are held in a high-impedance state to assure t he drivers remain off. the following input conditions must be met before the ISL8102 is released from shutdown mode. 1. the bias voltage applied at vcc must reach the internal power-on reset (por) risi ng threshold. once this threshold is reached, proper operation of a ll aspects of the ISL8102 is guaranteed. hyst eresis between the rising and falling thresholds assure that once enabled, the ISL8102 will not inadvertently turn off unless the bias voltage drops substantially (see electrical specifications on page 5). c boot_cap q gate ? v boot_cap -------------------------------------- ? q gate q g1 pvcc ? v gs1 ---------------------------------- n q1 ? = (eq. 11) 50nc 20nc figure 10. bootstrap capacitance vs boot ripple voltage ? v boot_cap (v) c boot_cap ( f) 1.6 1.4 1.2 1. 0.8 0.6 0.4 0.2 0.0 0.3 0.0 0.1 0.2 0.4 0.5 0.6 0.9 0.7 0.8 1.0 q gate = 100nc
ISL8102 fn9247 rev 1.00 page 15 of 27 july 28, 2008 2. the voltage on enll must be above 0.66v. the en input allows for power sequencing between the controller bias voltage and another voltage rail. the enable comparator holds the ISL8102 in shutdown until the voltage at enll rises above 0.66v. the enable comparator has 100mv of hysteresis to prevent bounce. 3. the driver bias voltage appl ied at the pvcc pins must reach the internal power-on reset (por) rising threshold. in order for the ISL8102 to begin operation, pvcc is the only pin that is required to have a voltage applied that exceeds por. hysteresis bet ween the rising and falling thresholds assure that once enabled, the ISL8102 will not inadvertently turn off unless the pvcc bias voltage drops substantially (seeelectrica l specifications on page 5). when each of these conditions is true, the controller immediately begins the soft-start sequence. soft-start during soft-start, th e dac voltage ramps linearly from zero to the programmed level. t he pwm signals remain in the high-impedance state until th e controller de tects that the ramping dac level has reach ed the output-voltage level. this protects the system again st the large, negative inductor currents that would otherwise occur when starting with a pre-existing charge on the output as the controller attempted to regulate to zero volts at t he beginning of t he soft-start cycle. the output soft-start time, t ss , begins with a delay period equal to 64 switching cycles after the enll has exceeded its por level, followed by a linear ramp with a rate determined by the switching period, 1/f sw . for example, a regulator with 450khz switching frequency having ref voltage set to 1.2v has t ss equal to 3.55ms. a 100mv offset exist s on the remote-sens e amplifier at the beginning of soft-start and ramps to zero during the first 640 cycles of soft-start (704 cycl es following en able). this prevents the large inrush curre nt that would otherwise occur should the output voltage start out with a slight negative bias. during the first 640 cycles of so ft-start (704 cycles following enable) the dac voltage increm ents the reference in 25mv steps. the remainder of soft-s tart sees the dac ramping with 12.5mv steps. the ISL8102 also has the abi lity to start up into a pre-charged output as shown i n figure 12, wit hout causing any unnecessary disturbance. the fb pin is monitored during soft-start, and should i t be higher than the equivalent internal ramping reference vol tage, the output drives hold both mosfets off. once the in ternal ramping reference exceeds the fb pin potential, the output drives are enabled, allowing the output to ramp from the pre-charged level to the final level dictated by the reference setting. should the output be pre-charged to a level exceeding the reference setting, the output drives ar e enabled at the end of the soft-start period, leading to an abrupt correction in the outpu t voltage down to the reference set level fault monitoring and protection the ISL8102 actively monitors ou tput voltage and current to detect fault conditions. faul t monitors trigger protective measures to preven t damage to the sensitive load. one common power good indicator is provided for linking to external system monitors. the schematic in figure 13 outlines the interaction between the fault monitors and the power-good signal. figure 11. power sequencing using threshold- sensitive enable (enll) function - + 0.66v external circuit ISL8102 internal circuit enll +12v por circuit 10.7k ? 1.40k ? enable comparator soft-start and fault logic vcc pvcc t ss 64 dac + 1280 ? f sw -------------------------------------------- = (eq. 12) figure 12. soft-start waveforms for ISL8102-based multi-phase converter enll (5v/div) v out (0.5v/div) gnd> t1 gnd> t2 t3 output precharged below dac level output precharged above dac level
ISL8102 fn9247 rev 1.00 page 16 of 27 july 28, 2008 power-good signal the power-good pin (pgood) is a n open-drain logic output that transitions high when the converter is operating after soft-start. pgood pulls low dur ing shutdown and releases high after a successful soft-st art. pgood transitions low when an undervoltage, overvoltage, or overcurrent condition is detected or when the controlle r is disabled by a reset from enll or por. if after an undervo ltage or overvoltage event occurs the output returns to within under and overvoltage limits, pgood will return high. undervoltage detection the undervoltage threshold is set at 82% of the ref voltage. when the output voltage ( vsen-rgnd) is below the undervoltage threshold , pgood gets pulled low. no other action is taken by the c ontroller. pgood will return high if the output voltage rises above 85% of the ref voltage. overvoltage protection the ISL8102 constantly monitor s the difference between the vsen and rgnd voltages to detect if an overvoltage event occurs. during soft-start, whi le the dac/ref is ramping up, the overvoltage trip level is the higher of ref plus 150mv or a fixed voltage, v ovp . the fixed voltage, v ovp , is 1.67v. upon successful soft-start, the over voltage trip level is only ref plus 150mv. ovp releas es 50mv below its tr ip point if it was ref plus 150mv that tripped it, and releases 100mv below its trip point if it was the fixed voltage, v ovp , that tripped it. actions are taken by the ISL8102 to protect the load when an overvoltage condition occurs, unt il the output voltage falls back within set limits. at the inception of an overvoltage event, all lgate signals are commanded high, and the pg ood signal is driven low. this causes the controller to turn on the lower mosfets and pull the output voltage bel ow a level that might cause damage to the load. the lgate outputs remain high until vdiff falls to within the over voltage limits explained above. the ISL8102 will contin ue to protect the lo ad in this fashion as long as the overvol tage condition recurs. once an overvoltage conditi on ends the ISL8102 continues normal operation and pgood returns high. pre-por overvoltage protection prior to pvcc and vcc exc eeding their por levels, the ISL8102 is designed to protect the load from any overvoltage events that may occur. this is accomplished by means of an internal 10k ? resistor tied from phase to lgate, which turns on the lower mosfet to control the output voltage until the overvoltage event ceases or the input power supply cuts off. for complete prote ction, the low side mosfet should have a gate thresho ld well below the maximum voltage rating of the l oad/microprocessor. in the event that during norma l operation the pvcc or vcc voltage falls back below the por threshold, the pre-por overvoltage protection circuit ry reactivates to protect from any more pre-por overvoltage events open sense line protection in the case th at either of the remot e sense lines, vsen or gnd, become open, the ISL8102 is designed to detect this and shut down the controller . this event is detected by monitoring the voltage on the iref pin, which is a local version of v out sensed at the output s of the inductors. if vsen or rgnd become opened, vdiff falls, causing the duty cycle to increase and the output voltage on iref to increase. if the voltage on ir ef exceeds vdiff+1v, the controller will shut down. once the volt age on iref falls below vdiff+1v, the ISL8102 will restart at the beginning of soft-start. overcurrent protection the ISL8102 detects overcurre nt events by comparing the droop voltage, v droop , to the ocset voltage, v ocset , as shown in figure 13. the droop v oltage, set by the external current sensing circuitry, is proportional to the output curren t as shown in equation 8. a c onstant 100a flows through r ocset , creating the ocset vol tage. when the droop voltage exceeds the ocset voltage, the overcurrent protection circuitry activates . since the droop voltage is figure 13. power-good and protection circuitry - + dac + 150mv vsen - + 0.82 x dac ov uv pgood soft-start, fault and control logic - + oc - + isen iref isum icomp ocset r ocset + - v droop v ocset + - v ovp 100a ISL8102 internal circuitry - + rgnd x1 - + +1v vdiff droop* *connect droop to iref to disable the droop feature
ISL8102 fn9247 rev 1.00 page 17 of 27 july 28, 2008 proportional to the out put current, the overcurrent trip level, i max , can be set by selecting the proper value for r ocset , as shown in equation 13. once the output current exceeds t he overcurren t trip level, v droop will exceed v ocset , and a comparator will trigger the converter to begin overcurrent protection procedures. at the beginning of overcurrent shu tdown, the controller turns off both upper and lower mosf ets. the system remains in this state for a period of 4096 switching cycles. if the controller is still en abled at the end of this wait period, it will attempt a soft-start (as show n in figure 14). if the fault remains, the trip-retry cycles will continue indefinitely until either the controller is disabled or the fault is cleared. note that the energy delivered duri ng trip-retry cycling is much less than during full-load operati on, so there is no thermal hazard. general design guide this design guide is intended to provide a high-level explanation of the steps necessa ry to create a multiphase power converter. it is assumed t hat the reader i s familiar with many of the basic skills and techniques referenced in the following. in addition to this guide, intersil provides complet e reference designs that include sc hematics, bills of materials, and example board layouts for many applications. power stages the first step in designing a multiphase converter is to determine the number of p hases. this determination depends heavily on t he cost analysis which in turn depends on system constraints that differ from one design to the next. principally, the designer wi ll be concerned with whether components can be mounted on both sides of the circuit board, whether through-hole co mponents are permitted, the total board space available for power-supply circuitry, and the maximum amount of load current. generally speaking, the most economical soluti ons are those in which each phase handles betwe en 25 and 30a. all surface-mount designs will tend toward the lower end of this current range. if through-hole mosfets and inductors can be used, higher per-phase currents are possi ble. in cases where board space is the limiting constrai nt, current can be pushed as high as 40a per phase, but these designs require heat sinks and forced air to cool t he mosfets, inductors and heat-dissipating surfaces. mosfets the choice of mosfets depends on the current each mosfet will be required to conduct, the switching frequency, the capability of the mosfets to dissipate heat, and the availability and nature o f heat sinking and air flow. lower mosfet power calculation the calculation for the approx imate power loss in the lower mosfet can be simplified, since virtually all of the loss in the lower mosfet is due to c urrent conducted through the channel resistance (r ds(on) ). in equation 14, i m is the maximum continuous output current, i p-p is the peak-to-peak inductor current ( see equation 1), and d is the duty cycle (v out /v in ). an additional term can be ad ded to the lower-mosfet loss equation to account for additional loss accrued during the dead time when inductor current is flowing through the lower-mosfet body diode. this term is dependent on the diode forward voltage at i m , v d(on) , the switching frequency, f sw , and the length of dead times, t d1 and t d2 , at the beginning and the end of the lower-mosfet conduction interval respectively. the total maximum power dissipated in each lower mosfet is approximated by the summation of p low,1 and p low,2 . upper mosfet power calculation in addition to r ds(on) losses, a large portion of the upper-mosfet losses are du e to currents conducted across the input voltage (v in ) during switching. since a substantially higher portion of the upper-mosfet losses are dependent on switching frequency, the power calculation is more complex. upper mosfet l osses can be divided into separate components involving the upper-mosfet switching times, the lower-mosfet body-diode reverse-recovery charge, q rr , and the upper mosfet r ds(on) conduction loss. r ocset i max r comp dcr ?? 100 ? ar s ? ---------------------------------------------------------- = (eq. 13) 0a 0v output current figure 14. overcurrent behavior in hiccup mode output voltage p low 1 ? r ds on ?? i m n ----- - ?? ?? ?? 2 1d C ?? ? i lp p C , 2 1d C ?? ? 12 ----------------------------------------- + ? = (eq. 14) p low 2 ? v don ?? f sw i m n ----- - i pp C 2 ------------- - + ?? ?? t d1 ? i m n ----- - i pp C 2 ------------- - C ?? ?? t d2 ? + ?? = (eq. 15)
ISL8102 fn9247 rev 1.00 page 18 of 27 july 28, 2008 when the upper mosfet turns off, the lower mosfet does not conduct any portion of the inductor current until the voltage at the phase node falls below ground. once the lower mosfet begins conducti ng, the current in the upper mosfet falls to zero as the current in the lower mosfet ramps up to assume the full inductor current. in equation 16, the required time for t his commutation is t 1 and the approximated associated power loss is p up,1 . at turn on, the upper mosfet b egins to conduct and this transition occurs over a time t 2 . in equation 17, the approximate power loss is p up,2 . a third component involves the lower mosfet reverse-recovery charge, q rr . since the inductor current has fully commutated to the upper mosfet before the lower-mosfet body diode can recover all of q rr , it is conducted through the upper mosfet across vin. the power dissipated as a result is p up,3 . finally, the resistive part of t he upper mosfet is given in equation 19 as p up,4 . the total power dissipated by the upper mosfet at full load can now be approximated as the summation of the results from equations 16, 17, 18 and 19. since the power equations depend on mosfet p arameters, choosing the correct mosfets can be an it erative process involving repetitive solutions to the l oss equations for different mosfets and different switching frequencies. package power dissipation when choosing mosfets it is important to consider the amount of power being dissipa ted in the inte grated drivers located in the controller. since there are a total of two drive rs in the controller pa ckage, the total powe r dissipated by both drivers must be less than the maximum allowable power dissipation for the qfn package. calculating the power dissipation in the drivers for a desired application is critical to ensure safe operation. exceeding the maximum allowable power dissipation level will push the ic beyond the maximum recomm ended operating junction temperature of +12 5c. the maximum allowable ic power dissipation for the 5x5 qfn package is approximately 4w at room temperature. see ? layout considerat ions on page 24 for thermal transfer im provement suggestions. when designing the ISL8102 into an application, it is recommended that the followin g calculation is used to ensure safe operation at the desired frequency for the selected mosfets. the tota l gate drive po wer losses, p qg_tot , due to the gate char ge of mosfets and the integrated drivers internal circ uitry and their corresponding average driver current can be estimated with equations 20 and 21, respectively. in equations 20 and 21, p qg_q1 is the total upper gate drive power loss and p qg_q2 is the total lower gate drive power loss; the gate charge (q g1 and q g2 ) is defined at the particular gate to source d rive voltage pvcc in the corresponding mosfet data sheet; i q is the driver total quiescent current with no lo ad at both drive outputs; n q1 and n q2 are the number of upper and lower mosfets per phase, respectively; n phase is the number of active phases. the i q* vcc product is the quiescent power of the controller without capacitive load and is typically 75mw at 300khz. the total gate drive power l osses are dissipated among the resistive components along th e transition path and in the bootstrap diode. the portion of t he total power dissipated in the controller itself is the power dissipated in the upper driv e path resistance, p dr_up , the lower drive path resistance, p dr_low , and in the boot strap diode, p boot . the rest of the power will be dissi pated by the exter nal gate resistors (r g1 and r g2 ) and the internal gate resistors (r gi1 and r gi2 ) of the mosfets. figures 15 and 16 show the typical upper and lower gate drives turn-on transition path. the total power dissipation in the controller itself, p dr , can be roughly estimated as shown in equation 22. . p up 1 , v in i m n ----- - i pp C 2 ------------- - + ?? ?? t 1 2 ---- ?? ?? ?? f sw ??? ? (eq. 16) p up 2 , v in i m n ----- - i pp C 2 ------------- - C ?? ?? ?? t 2 2 ---- ?? ?? ?? f sw ??? ? (eq. 17) p up 3 , v in q rr f sw ?? = (eq. 18) p up 4 , r ds on ?? d i m n ----- - ?? ?? ?? 2 i pp C 2 12 ------------- - + ?? ? (eq. 19) p qg_tot p qg_q1 p qg_q2 i q vcc ? ++ = (eq. 20) p qg_q1 3 2 -- - q g1 pvcc f sw n q1 n phase ?? ??? = p qg_q2 q g2 pvcc f sw n q2 n phase ???? = -- - q g1 n ? q1 ? q g2 n q2 ? + ?? ?? n phase f sw i q + ?? = (eq. 21) p dr p dr_up p dr_low p boot i q vcc ? ?? +++ = (eq. 22) p dr_up r hi1 r hi1 r ext1 + -------------------------------------- r lo1 r lo1 r ext1 + ---------------------------------------- + ?? ?? ?? p qg_q1 3 --------------------- ? = p dr_low r hi2 r hi2 r ext2 + -------------------------------------- r lo2 r lo2 r ext2 + ---------------------------------------- + ?? ?? ?? p qg_q2 2 --------------------- ? = r ext1 r g1 r gi1 n q1 ------------- + = r ext2 r g2 r gi2 n q2 ------------- + = p boot p qg_q1 3 --------------------- =
ISL8102 fn9247 rev 1.00 page 19 of 27 july 28, 2008 current balancing component selection the ISL8102 senses the channel load current by sampling the voltage across the lower mosfet r ds(on) , as shown in figure 17. the isen pins ar e denoted isen1, and isen2. the resistors connected bet ween these pins and the respective phase nodes dete rmine the gains in the channel current balance loop. select values for these re sistors based on the room temperature r ds(on) of the lower mosfet s; the full-load operating current, i fl ; and the number of phases, n using equation 23. in certain circumsta nces, it may be neces sary to adjust the value of one or more isen resistors. when the components of one or more channels are inhibited from effectively dissipating their heat so that the affected channels run hotter than desired, choose new, smaller values of r isen for the affected phases (see channel current balance on page 10 ). choose r isen,2 in proportion to the desired decrease in temperature rise in order to c ause proportionally less current to flow in the hotter phase. in equation 24, make sure that ? t 2 is the desired temperature rise above the ambient temperature, and ? t 1 is the measured temperature rise above the am bient temperature. while a single adjustment according to equation 24 is usually sufficient, it may occasio nally be necessary to adjust r isen two or more times to achie ve optimal thermal balance between all channels. load line regulation component selection (dcr current sensing) for accurate load line regulati on, the ISL8102 senses the total output current by detect ing the voltage across the output inductor dcr of each channel (as described in load-line (droop) regulation on page 12). as figure 18 illustrates, an r-c network is required to accurately sense the inductor dcr voltage and con vert this information into a droop voltage, which is pr oportional to the total output current. choosing the components for this current sense network is a two step process. first, r comp and c comp must be chosen so that the time constant of this r comp -c comp network matches the time constant of the inductor l/dcr. then the resistor r s must be chosen to set the current sense network gain, obtaining the desired full load droop voltage. follow the steps be low to choose the component values for this r-c network. 1. choose an arbitrary value for c comp . the recommended value is 0.01f. 2. plug the inductor l and dcr component values, and the values for c comp chosen in step 1, i nto equation 25 to calculate the value for r comp . 3. use the new value for r comp obtained from equation 25, as well as the desired full load current, i fl , full load droop voltage, v droop , and inductor dcr in equation 26 to calculate the value for r s . figure 15. typical upper-gate drive turn-on path figure 16. typical lower-gate drive turn-on path q1 d s g r gi1 r g1 boot r hi1 c ds c gs c gd r lo1 phase pvcc ugate pvcc q2 d s g r gi2 r g2 r hi2 c ds c gs c gd r lo2 lgate figure 17. ISL8102 internal and external current- sensing circuitry isen(n) r isen v in channel n upper mosfet channel n lower mosfet - + i l x r ds on ?? i l ISL8102 r isen r ds on ?? 50 10 6 C ? ----------------------- i fl n ------- - ? = (eq. 23) r isen 2 , r isen ? t 2 ? t 1 ---------- ? = (eq. 24) r comp l dcr c comp ? --------------------------------------- = (eq. 25) r s i fl v droop ------------------------ - r comp dcr ?? = (eq. 26)
ISL8102 fn9247 rev 1.00 page 20 of 27 july 28, 2008 due to errors in the inductan ce or dcr it may be necessary to adjust the value of r comp to match the ti me constants correctly. the effects of time constant mismatch can be seen in the form of droop overshoo t or undershoot during the initial load transient spike, as shown in figure 19. follow the steps below to ensure the r-c and inductor l/dcr time constants are matched accurately. 1. capture a transient event with the oscilloscope set to about l/dcr/2 (sec/div). for example, with l = 1h and dcr = 1m ? , set the oscillosc ope to 500s/div. 2. record ? v 1 and ? v 2 as shown in figure 19. 3. select a new value, r comp,2 , for the time constant resistor based on the original value, r comp,1 , using equation 27. 4. replace r comp with the new value and check to see that the error is corrected. repeat the procedure if necessary. after choosing a new value for r comp , it will most likely be necessary to adjust the value of r s to obtain the desired full load droop voltage. use equation 26 to obtain the new value for r s . compensation the two opposing goals of c ompensating the voltage regulator are stability and speed. depending on whether the regulator employs the optional load-line regulation (as described in load line regu lation component selection (dcr current sensing) on page 19 ) there are two distinct methods for achieving these goals. compensating the load-line regulated converter the load-line regulated con verter behaves in a similar manner to a peak current mode controller because the two poles at the output filter l-c r esonant frequency split with th e introduction of curre nt information into t he control loop. the final location of the se poles is determ ined by the system function, the gain of the current signal, a nd the value of the compensation components, r 2 and c 1 . since the system poles and zero are affected by the values of the components that are m eant to compensate them, the solution to the system equation becomes fairly complicated. fortunately, there is a simple approximation that comes very close to an optimal solution. treating the system as though it were a voltage-mode regulator , by compensating the l-c figure 18. dcr sensing configuration - + icomp dcr l inductor v out c out i l 1 - + v l (s) dcr l inductor phase1 phase2 i l 2 r s r s r comp c comp isum iref ISL8102 - + v droop i out droop r comp 2 ? r comp 1 ? v 1 ? v 2 ? ---------- ? = (eq. 27) figure 19. time constant mismatch behavior ? v 1 v out i tran ? v 2 ? i figure 20. compensation configuration for load-line regulated ISL8102 circuit ISL8102 comp c 1 r 2 r 1 fb vdiff c 2 (optional)
ISL8102 fn9247 rev 1.00 page 21 of 27 july 28, 2008 poles and the esr zero of the v oltage mode approximation, yields a solution that is always stable with very close to idea l transient performance. the feedback resistor, r 1 , has already been chosen as outlined in load line regula tion component selection (dcr current sensing) on page 19 . select a target bandwidth for the co mpensated system, f 0 . the target bandwidth must be large enough to assure adequate transient performance, but smaller than 1/3 of the per-channel switching frequency. the values of the compensation components depend on the relationships of f 0 to the l-c pole frequency a nd the esr zero frequency. for each of the following three, t here is a separate set of equations for the compensation components. in equation 28, l is the per-channel filter inductance divided by the number of active channels ; c is the sum total of all output capacitors; esr is the equivalent series resistance of the bulk output filter capacitance; and v osc is the peak-to-peak sawtooth signal am plitude as described in the electrical specifications on page 5. once selected, the compensation values in equation 28 assure a stable converter with reasonable transient performance. in most cases, tr ansient performance can be improved by making adjustments to r 2 . slowly increase the value of r 2 while observing the transient performance on an oscilloscope until no further improvement is noted. normally, c 1 will not need adjustmen t. keep the value of c 1 from equation 28 unless some per formance issue is noted. the optional capacitor c 2 , is sometimes ne eded to bypass noise away from the pwm comparator (see figure 20). keep a position available for c 2 , and be prepared to install a high frequency capacitor of between 22pf and 150pf in case any leading edge jitter problem is noted. compensating the converter operating without load-line regulation the ISL8102 multi-phase conver ter operating without load line regulation behaves in a similar manner to a voltage-mode controller. this section highlights the design consideration for a voltage-mode controller requiring external compensation. to address a br oad range of app lications, a type-3 feedback network is recommended (see figure 21). figure 22 highlights the volt age-mode control loop for a synchronous-rectified buck co nverter, applicable, with a small number of adjustment s, to the multiphase ISL8102 circuit. the output voltage (v out ) is regulated to the reference voltage, vref, level . the error amp lifier output (comp pin voltage) is compar ed with the oscillator (osc) modified saw-tooth wave to provide a pulse-width modulated wave with an amplitude of v in at the phase node. the pwm wave is smoothed by the output filter (l and c). the output filter capacitor banks equ ivalent series resistance is represented by the series resistor esr. the modulator transfe r function is the small-signal transfer function of v out /v comp . this function is dominated by a dc gain, given by d max v in /v osc , and shaped by the output filter, with a double pole break frequency at f lc and a zero at f ce . for the purpose of this analysis, l and dcr represent the individual channel inductance and its dcr divided by 2 (equivalent para llel value of the two output inductors), while c and esr r epresents the total output capacitance and its equivalent series resistance. 1 2 ? lc ? ? --------------------------- f 0 > r 2 r 1 2 ? f 0 v osc lc ? ?? ? 0.66 v in ? ----------------------------------------------------------- - ? = c 1 0.66 v in ? 2 ? v osc r 1 f 0 ??? ------------------------------------------------ - = case 1: 1 2 ? lc ? ? --------------------------- f 0 1 2 ? c esr ?? --------------------------------- < ? r 2 r 1 v osc 2 ? ?? 2 f 0 2 lc ???? 0.66 v in ? --------------------------------------------------------------- - ? = c 1 0.66 v in ? 2 ? ?? 2 f 0 2 v osc r 1 lc ? ?? ? ? --------------------------------------------------------------- ---------------- - = case 2: f 0 1 2 ? c esr ?? --------------------------------- > r 2 r 1 2 ? f 0 v osc l ?? ? 0.66 v in esr ?? ----------------------------------------------- ? = c 2 0.66 v in esr c ?? ? 2 ? v osc r 1 f 0 l ???? -------------------------------------------------------------- - = case 3: (eq. 28) figure 21. compensation configuration for non-load-line regulated ISL8102 circuit ISL8102 comp c 1 r 2 r 1 fb vdiff c 2 r 3 c 3 f lc 1 2 ? lc ? ? --------------------------- = f ce 1 2 ? c esr ?? --------------------------------- = (eq. 29)
ISL8102 fn9247 rev 1.00 page 22 of 27 july 28, 2008 the compensation network consists of the error amplifier (internal to the ISL8102) and the external r 1 -r 3 , c 1 -c 3 components. the goal of the compensation network is to provide a closed loop transfer function with high 0db crossing frequency (f 0 ; typically 0.1 to 0.3 of f sw ) and adequate phase margin (better than 45). phase margin is the difference between the closed loop phase at f 0db and +180. equations 29 to 35 relate the compensation networks poles, zeros and gain to the components (r 1 , r 2 , r 3 , c 1 , c 2 , and c 3 ) in figures 20 and 21. use the following guidelines for locating the poles and zeros of the compensation network: 1. select a value for r 1 (1k ? to 5k ? , typically). calculate value for r 2 for desired converter bandwidth (f 0 ). if setting the output voltage to be equal to the reference set voltage as shown in figure 22, the design procedure can be followed as presented. h owever, when setting the output voltage via a resistor divider placed at the input of the differential amplifier (as shown in figure 6), in order to compensate for the att enuation introduced by the resistor divider, the obtained r 2 value needs be multiplied by a factor of (r p1 + r s1 )/r p1 . the remainder of the calculations remain unchanged, as long as the compensated r 2 value is used. 2. calculate c 1 such that f z1 is placed at a fraction of the f lc , at 0.1 to 0.75 of f lc (to adjust, change the 0.5 factor to desired number). the higher the quality factor of the output filter and/or the h igher the ratio f ce /f lc , the lower the f z1 frequency (to maximize phase boost at f lc ). 3. calculate c 2 such that f p1 is placed at f ce . 4. calculate r 3 such that f z2 is placed at f lc . calculate c 3 such that f p2 is placed below f sw (typically, 0.5 to 1.0 times f sw ). f sw represents the per-channel switching frequency. change the numeric al factor to ref lect desired placement of this pole. placement of f p2 lower in frequency helps reduce the gain of the compensation network at high frequency, in turn reducing the hf ripple component at the comp pin and minimizing resultant duty cycle jitter. it is recommended that a mathematical model is used to plot the loop response. check t he loop gain against the error amplifiers open-loop gain. verif y phase margin results and adjust as necessary . equation 34 descri be the frequency response of the modulator (g mod ), feedback compensation (g fb ) and closed-loop response (g cl ) : compensation break f requency equations figure 23 shows an a symptotic plot of t he dc/dc converters gain vs. frequency. the actual m odulator gain has a high gain peak dependent on the qu ality factor (q) of the output filter, which is not shown. using the above guidelines should yield a compensation gain similar to t he curve plotted. the open loop error amplifier gain bounds the compensation gain. check the figure 22. voltage-mode buck converter compensation design - + e/a vref comp c 1 r 2 r 1 fb c 2 r 3 c 3 l c v in pwm circuit half-bridge drive oscillator esr external circuit ISL8102 v out v osc dcr ugate phase lgate - + vdiff vsen rgnd r 2 v osc r 1 f 0 ?? d max v in f lc ?? --------------------------------------------- = (eq. 30) c 1 1 2 ? r 2 0.5 f lc ?? ? ---------------------------------------------- - = (eq. 31) c 2 c 1 2 ? r 2 c 1 f ce 1 C ??? -------------------------------------------------------- = (eq. 32) r 3 r 1 f sw f lc ------------ 1 C --------------------- - = c 3 1 2 ? r 3 0.7 f sw ?? ? ------------------------------------------------ - = (eq. 33) g mod f ?? d max v in ? v osc ----------------------------- - 1sf ?? esr c ?? + 1sf ?? esr dcr + ?? c ?? s 2 f ?? lc ?? ++ --------------------------------------------------------------- -------------------------------------------- ? = g fb f ?? 1sf ?? r 2 c 1 ?? + sf ?? r 1 c 1 c 2 + ?? ?? ---------------------------------------------------- ? = 1sf ?? r 1 r 3 + ?? c 3 ?? + 1sf ?? r 3 c 3 ?? + ?? 1sf ?? r 2 c 1 c 2 ? c 1 c 2 + -------------------- - ?? ?? ?? ?? + ?? ?? ?? ? --------------------------------------------------------------- ---------------------------------------------------------- g cl f ?? g mod f ?? g fb f ?? ? = where s f ?? ? 2 ? fj ?? = (eq. 34) f z1 1 2 ? r 2 c 1 ?? ------------------------------ - = f z2 1 2 ? r 1 r 3 + ?? c 3 ?? ------------------------------------------------- = f p1 1 2 ? r 2 c 1 c 2 ? c 1 c 2 + -------------------- - ?? -------------------------------------------- - = f p2 1 2 ? r 3 c 3 ?? ------------------------------ - = (eq. 35)
ISL8102 fn9247 rev 1.00 page 23 of 27 july 28, 2008 compensation gain at f p2 against the capabilit ies of the error amplifier. the closed loop gain, g cl , is constructed on the log-log graph of figure 23 b y adding the modulator gain, g mod (in db), to the feedba ck compensation gain, g fb (in db). this is equivalent to multi plying the modulator transfer function and the compensation transfer function and then plotting the resulting gain. a stable control loop has a gai n crossing with close to a -20db/decade slope and a phase margin greater than 45. include worst case component variations when determining phase margin. the mathemati cal model presented makes a number of approximations and is generally not accurate at frequencies approaching or exceeding half the switching frequency. when designing com pensation netwo rks, select target crossover frequencies in the range of 1 0% to 30% of the per-channel switching frequency, f sw . output filter design the output inductors and the output capacitor bank together to form a low-pass filter responsible for smoothing the pulsating voltage at the phase nodes. the output filter also must provide the transient ene rgy until the regulator can respond. because it has a lo w bandwidth compared to the switching frequency, the outpu t filter limits the system transient response. the output capacitors must supply or sink load current while the curre nt in the output inductors increases or decreases to meet the demand. in high-speed converters, the output capacitor bank is usually the most costly (and often the largest) part of the circuit. output filter design begins with minimizing the cost of this pa rt of the circuit. the critical load parameters in choosing the output capacitors are the maximum size of the load step, ? i, the load-current slew rate, di/dt , and the maximum allowable output-voltage deviation under transient loading, ? v max . capacitors are characterized ac cording to their capacitance, esr, and esl (equivalent series inductance). at the beginning of the load trans ient, the outpu t capacitors supply all of the tr ansient current. the output voltage will initially deviate by an amount approximated by the voltage drop across the esl. as the lo ad current increases, the voltage drop across the esr increases linearly until the load current reaches its final value. the capacitors selected must have sufficiently low esl and esr so that the total output-voltage deviation is less than the allowable maximum. neglecting the contribution of inductor current and regulator response, the output voltage initially deviates by an amount as shown in equation 36. the filter capacitor must have sufficient ly low esl and esr so that ? v < ? v max . most capacitor solutions rely on a mixture of high frequency capacitors with relatively low capacitance in combination with bulk capacitors having h igh capacitance but limited high-frequency performance. minimizing the esl of the high-frequency capacitors allow s them to support the output voltage as the current increases. minimizing the esr of the bulk capacitors allows them to supply the increased current with less output voltage deviation. the esr of the bulk capacitors also creates the majority of the output-voltage ri pple. as the bulk capacitors sink and source the inductor ac ripple cu rrent (see interleaving on page 9 and equation 2), a volt age develops across the bulk capacitor esr equal to i c,pp (esr). thus, once the output capacitors are selected, the maximum allowable ripple voltage, v pp(max) , determines the lower limit on the inductance. since the capacitors are supplying a decreasing portion of the load current while the regulator rec overs from the t ransient, the capacitor voltage becomes slight ly depleted. the output inducto rs must be capable of assuming the entire load curr ent before the output voltage decreases more than ? v max . this places an upper limit on inductance. equation 38 gives the upper limi t on l for the cases when the trailing edge of the current trans ient causes a greater output- voltage deviation than the l eading edge. equation 39 addresses the leading edge. normally, the trailing edge dictates the sele ction of l because duty cycles are usu ally less than 50% . nevertheles s, both inequalities should be evaluated, and l should be selected based on the lower of the two res ults. in each equation, l is t he per-channel inductance, c is the total output capacitance, and n is the number of active channels. 0 f p1 f z2 open loop e/a gain f z1 f p2 f lc f ce compensation gain gain frequency modulator gain figure 23. asymptotic bod e plot of converter gain closed loop gain 20 r2 r1 ------- - ?? ?? log log log f 0 g mod g fb g cl 20 d max v ? in v osc --------------------------------- log ? v esl ?? di dt ---- - ? esr ??? i ? + ? (eq. 36) l esr ?? v in nv ? out C ?? ?? v out ? f sw v in v pp max ?? ?? --------------------------------------------------------------- ---- - ? (eq. 37) l 2ncv o ??? ? i ?? 2 --------------------------------- ? v max ? iesr ? ?? C ? ? (eq. 38) l 1.25 ?? nc ?? ? i ?? 2 --------------------------------- - ? v max ? i esr ? ?? C v in v o C ?? ?? ?? ? (eq. 39)
ISL8102 fn9247 rev 1.00 page 24 of 27 july 28, 2008 switching frequency there are a number of variabl es to consider when choosing the switching frequency, as there are considerable effects on the upper mosfet loss calculation. these effects are outlined in mosfets on page 17, and they es tablish the upper limit for the s witching frequency. the lower limit is established by the requirement for fast transient response and small output-voltage ripple as outlined in output filter design on page 23. choose the lowest switching frequency that allows the regulator to m eet the transient-response requirements. switching frequency is determi ned by the selection of the frequency-setting resistor, r fs . figure 24 and equation 40 are provided to assist in sele cting the correct value for r fs . input capacitor selection the input capacitors are resp onsible for sourcing the ac component of the input curre nt flowing into the upper mosfets. their rms current cap acity must be sufficient to handle the ac component of the current drawn by the upper mosfets which is r elated to dut y cycle and the number of active phases. for a two-phase design, use figure 25 to determine the input-capacitor rm s current requirement set by the duty cycle, maximum sustai ned output current (i o ), and the ratio of the peak-to-peak inductor current (i l,p-p ) to i o . select a bulk capacitor with a ripple current rating which will minimize the total number of input capacitors required to support the rms current calculated. the vo ltage rating of the capacitors should also be at least 1.25 t imes greater than the maximum input voltage. figure 26 provides the same input rms current information for single- phase designs. use the same approach for selecting the bu lk capacitor type and number. low esl, high-frequency ceramic capacitors are needed in addition to the input bulk capacitors to suppress leading and falling edge voltage spikes. the spikes result from the high current slew rate produced by the upper mosfet turn on and off. place them as close as possible to each upper mosfet drain to minimize board parasi tics and maximize suppression. layout considerations mosfets switch very fast and efficiently. the speed with which the current transitions from one devic e to another causes voltage spikes across the interconnecting impedances and parasitic circuit elements. these voltage spikes can degrade efficiency, r adiate noise into the circuit and lead to device overvoltage stress. careful component layout and printed circuit de sign minimizes the voltage r fs 10 10.61 1.035 f sw ?? log ? C ?? = (eq. 40) figure 24. r fs vs switching frequency 100k 200k 500k 1m 2m switching frequency (hz) r fs value (k ? ) 10 20 50 100 200 figure 25. normalized input-capacitor rms current for 2-phase converter 0.3 0.1 0 0.2 input-capacitor current (i rms/ i o ) 00.4 1.0 0.2 0.6 0.8 duty cycle (v in/ v o ) i l,p-p = 0 i l,p-p = 0.5 i o i l,p-p = 0.75 i o figure 26. normalized input-capacitor rms current for single-phase converter 00.4 1.0 0.2 0.6 0.8 duty cycle (v in /v o ) input-capacitor current (i rms /i o ) 0.6 0.2 0 0.4 i l,p-p = 0 i l,p-p = 0.5 i o i l,p-p = 0.75 i o
fn9247 rev 1.00 page 25 of 27 july 28, 2008 ISL8102 intersil products are manufactured, assembled and tested utilizing iso9001 quality systems as noted in the quality certifications found at www.intersil.com/en/suppor t/qualandreliability.html intersil products are sold by description on ly. intersil may modify the circuit design an d/or specifications of products at any time without notice, provided that such modification does not, in intersil's sole judgment, affect the form, fit or function of the product. accordingly, the reader is cautioned to verify that datasheets are current before placing orders. information fu rnished by intersil is believed to be accu rate and reliable. however, no responsib ility is assumed by intersil or its subsidiaries for its use; nor for any infrin gements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com for additional products, see www.intersil.com/en/products.html ? copyright intersil americas ll c 2005-2008. all rights reserved. all trademarks and registered trademarks are the property of their respective owners. spikes in the converter. consider, as an example, the turnoff transition of the upper pwm mo sfet. prior to turnoff, the upper mosfet was carrying channel current. during the turnoff, current stops flowin g in the upper mosfet and is picked up by the lower mosfet. any inductance in the switched current path generates a large voltage spike during the switching interval. carefu l component sel ection, tight layout of the critical components, and short, wide circuit traces minimize the magni tude of voltage spikes. there are two sets of crit ical components in a dc/dc converter using a ISL8102 controller. the power- components are the most critica l because they switch large amounts of energy. next are small signal components that connect to sensitive nodes o r supply critical bypassing current and signal coupling. it is important to have a symmetri cal layout, preferably with the controller equidistantly located from the two power trains it controls. equally important are the gate drive lines (ugate, lgate, phase): since they dri ve the power train mosfets using short, high current pulses, it is important to size them as large and as short as possibl e to reduce their overall impedance and inductance. extra care should be given to the lgate traces in particular s ince keeping the impedance and inductance of these tr aces helps to significantly reduce the possibility of shoot-through. equidistant placement of the controller to the two power tr ains also helps keeping these traces equally short (equal im pedances, resulting in similar driving of both sets of mosfets). the power components should be placed first. locate the input capacitors close to the power swi tches. minimize the length of the connections between the input capacitors, c in , and the power switches. locate the output inductors and output capacitors between the mosfet s and the load. locate the high-frequency decoupling capacitors (ceramic) as close as practicable to the decoupling target, making use of the shortes t connection paths to any interna l planes, such as vias to gnd immediately next, or even ont o the capacitor solder pad. the critical small components include the bypa ss capacitors for vcc and pvcc. locate th e bypass capacitors, cbp, close to the device. it is espec ially important t o locate the components associated with the feedback circuit close to their respective controller pins, since t hey belong to a high-impedance circuit loop, sen sitive to emi pick-up. it is also important to place curren t sense components close to their respective pins on the ISL8102, including the risen resistors, rs, rcomp, ccomp. f or proper curr ent sharing route two separate symmetrical as possible traces from the corresponding phase n ode for each risen. a multi-layer printed circuit board is recommended. figure 27 shows the connections of the critical components for the converter. note that capacitors c xxin and c xxout could each represent numerous phy sical capacitors. dedicate one solid layer, usually the one underneath the component side of the board, for a ground plane and make all critical component ground connections with vias to this layer. dedicate another solid layer as a power plane and break this plane into smaller islands of common voltage leve ls. keep the metal runs from the phase terminal to inductor l out short. the power plane should support the input power and output power nodes. use copper filled polygons on the top and bottom circuit layers for the phase nodes. use the remainin g printed circuit layers for small signal wiring. the wiring traces from the ic to the mosfets gates and sources should be sized to carry at least one ampere of curren t (0.02 to 0.05).
ISL8102 fn9247 rev 1.00 page 26 of 27 july 28, 2008 via connection to ground plane island on power plane layer island on circuit plane layer key figure 27. printed circuit board power planes and islands heavy trace on ci rcuit plane layer +12v +12v load c boot1 r isen1 r isen2 c boot2 c bin1 (c hfout ) c bout c hf1 c bin2 locate close to ic locate near load; (minimize connection path) locate near switchi ng transistors; (minimize conne ction path) (minimize connection path) c hf2 c comp r comp r s r s r ocset pgood vdiff fb comp vcc isen1 ISL8102 ref1 fs ofst ref phase1 ugate1 boot1 lgate1 isen2 phase2 ugate2 boot2 lgate2 isum icomp iref vsen rgnd ocset ref0 +5v pvcc enll +12v gnd ovp 2ph dac droop c 1 r 2 c 2 r 1 c hf0 r ofst r ref c ref c sum to pvcc c hf01 l out1 l out2 r fs
ISL8102 fn9247 rev 1.00 page 27 of 27 july 28, 2008 package outline drawing l32.5x5 32 lead quad flat no-lead plastic package rev 2, 02/07 located within the zone indicate d. the pin #1 identifier may be unless otherwise specified, t olerance : decimal 0.05 tiebar shown (if present) i s a non-functional feature. the configuration of the pin #1 identifier is optional, but mus t be between 0.15mm and 0.30mm from the terminal tip. dimension b applies to the metallized terminal and is measured dimensions in ( ) for reference only. dimensioning and tolerancing c onform to amse y14.5m-1994. 6. either a mold or mark feature. 3. 5. 4. 2. dimensions are in millimeters. 1. notes: bottom view detail "x" side view typical recommended land pattern top view 5.00 a 5.00 b index area pin 1 6 (4x) 0.15 32x 0.40 0.10 4 a 32x 0.23 m 0.10 c b 16 9 4x 0.50 28x 3.5 6 pin #1 index area 3 .10 0 . 15 0 . 90 0.1 base plane see detail "x" seating plane 0.10 c c 0.08 c 0 . 2 ref c 0 . 05 max. 0 . 00 min. 5 ( 3. 10 ) ( 4. 80 typ ) ( 28x 0 . 5 ) (32x 0 . 23 ) ( 32x 0 . 60) + 0.07 - 0.05 17 25 24 8 1 32

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